Paper Presentation On A Fast Simulation Approach (VLSI) For ECE

A Fast Simulation Approach for Inductive Effects of VLSI Interconnects

ABSTRACT: Modeling on-chip inductive effects for interconnects of multiGHz microprocessors remains challenging. SPICE simulation of these effects is very slow because of the large number of mutual inductances. Meanwhile, ignoring the nonlinear behavior of drivers in a fast linear circuit simulator results in large errors for the inductive effect. In this paper, a fast and accurate time-domain transient analysis approach is presented, which captures the non-linearity of circuit drivers, the effect of non-ideal ground and de-coupling capacitors in a bus structure. The proposed method models the non-linearity of drivers in conjunction with specific bus geometries. Linearized waveforms at each driver output are incorporated into an interconnect reduced-order simulator for fast transient simulation. In addition, non-ideal ground and de-coupling capacitor models enable accurate signal and ground bounce simulations. Results show that this simulation approach is upto 68x faster than SPICE while maintaining 95% accuracy.