Creating High-Speed Memory Interfaces with Virtex-II and Virtex-II Pro FPGAs
Designing high-speed memory interfaces is a challenging task. Xilinx has invested time and effort to make it simple to design such interfaces using the Virtex-II™ and Virtex-II Pro™ FPGAs.This application note discusses the challenges presented by this task together with various techniques that can be used to overcome them, while illustrating the key concepts in implementing any memory interface. The interface speed is 200 MHz. High-speed memory interfaces are typically source-synchronous and double data rate. In a source-synchronous design, the clocks are generated and transmitted along with the data, as shown in Figure 1. The data is typically received High-speed controllers and interfaces are challenging to design. Designing high-speed memory interfaces are particularly challenging due to various factors. Some of the key challenges are • Source-synchronous data transmit (data write function). • Source-synchronous data receive (data read function).While these functions are common in all high-speed interfaces, memory interfaces make it particularly challenging due to the following factors:• Single-ended standards. Memories typically use HSTL or SSTL type input/output standard.
